Tokyo, Japan and Albany, NY, (Nov.6, 2007) Tokyo Electron, Ltd. (TEL) has become the first semiconductor supplier company to join SEMATECHs 3D Interconnect Program, teaming with several leading chip-makers who are the programs founding members.



TELs agreement with SEMATECH, formalized at a recent signing ceremony in Tokyo, adds significant resources to SEMATECHs effort aimed at evolving the traditional copper/low-k interconnect technology to three-dimensional chip stacking, including through silicon vias (TSVs) as interconnects. The 3D Program, launched in 2005 with the participation of SEMATECHs existing member companies, was opened earlier this year to equipment and materials suppliers, fabless companies, chip-makers, assembly and packaging companies, and others.



3D integration will be a key driver of semiconductor density, performance, functionality, and productivity, said Sitaram Arkalgud, program director. To realize the full potential of 3D, we will need the collaboration of a broader cross-section of industry participants. TELs investment in our program is a major step in that direction.



3D integration will become an indispensable technology in the near future, as device scaling becomes more and more difficult and as end products in electronics become more diversified, said Masayuki Tomoyasu, Senior Vice President of TEL Technology Center, America, LLC. SEMATECHs 3D Interconnect Program has broadly surveyed the industry to understand technical and economic requirements and has gathered technological knowledge to realize those requirements. SEMATECH provides the most suitable development foundation for TEL to apply our current wafer process knowledge to 3D-TSV processes. Together we will contribute to industry-wide implementation of 3D.



3D-TSV technology requires bonding semiconductor wafers and/or dies and uses deep TSVs for interconnects. The goal of SEMATECHs program is to enable high-volume manufacturing of 3D-TSV chips by its members with an optimum combination of cost, functionality, performance, and power consumption. When ready for volume manufacturing, 3D-TSV will provide cost-effective ways to integrate diverse CMOS technologies, and eventually link CMOS chips with emerging technologies such as micro-electromechanical systems (MEMS) and bio-chips.



Prior to joining the 3D initiative, TEL was engaged with SEMATECH in a joint development program to address early development challenges in 3D-TSV, including deep-silicon reactive ion etching (RIE), cost modeling, process benchmarking, standards development, and technology roadmapping.

TELs extensive experience in the areas of front-end and back-end processing and MEMs technology has proven invaluable to these early efforts, said Arkalgud. He added that SEMATECH is nearing completion of 3D program membership agreements with additional companies.







For 20 years, SEMATECH (www.sematech.org) has set global direction, enabled flexible collaboration, and bridged strategic R&D to manufacturing. Today, we continue accelerating the next technology revolution with our nanoelectronics and emerging technology partners.